Method for treating semiconductor processing components and components formed thereby

ABSTRACT

A semiconductor processing component formed of SiC, wherein an outer surface portion of the component has a surface impurity level that is not greater than ten times a bulk impurity level of the outer surface portion.

CROSS-REFERENCE TO RELATED APPLICATION(S)

[0001] This application is a continuation-in-part application of U.S.10/414,563, filed Apr. 15, 2003, and claims priority thereto under 35USC 120.

BACKGROUND

[0002] 1. Field of the Invention

[0003] The present invention is generally related to methods fortreating semiconductor processing components for use in a semiconductorfabrication environment, as well as semiconductor processing componentsformed thereby.

[0004] 2. Description of the Related Art

[0005] In the art of semiconductor processing, typically integratedcircuit devices are formed through various wafer processing techniques,in which semiconductor (principally silicon) wafers are processedthrough various stations or tools. Processing operations include, forexample, high temperature diffusion, thermal processing, ion implant,annealing, photolithography, polishing, deposition, etc. As newgeneration semiconductor devices are developed, an intense demandcontinues to exist in the industry to achieve better purity levelsduring such processing operations. In addition, there continues to be anintense driving force in transitioning to larger semiconductor wafers.Currently, the semiconductor industry is undergoing a transition from200 mm to 300 mm wafers. The desire for superior purity levels andlarger wafers introduces further integration challenges for nextgeneration processing.

[0006] U.S. Pat. No. 6,093,644 discloses a process in which an oxidationstep is carried out, followed by oxide layer removal. However, thetechniques disclosed therein do not adequately address certaincontamination issues, and appear to focus on global impurity levels ofthe component, and not impurity levels along critical portions of thecomponent. Further, the technology appears limited to restoringpre-machined purity levels to the component in the post-machined state.

[0007] Despite improvements in the industry to address next generationpurity concerns as well as handling issues associated with larger-sizedsemiconductor wafers, a need continues to exist in the art for furtherimproved semiconductor processing components, methods for forming suchcomponents, and methods for processing semiconductor wafers.

SUMMARY

[0008] According to one aspect of the invention, a semiconductorprocessing component is provided, the component comprising siliconcarbide, wherein an outer surface portion of the component has a surfaceimpurity level and a bulk impurity level. Preferably, the surfaceimpurity level is not greater than ten times the bulk impurity level.

[0009] According to another embodiment, a method for treating asemiconductor processing component is provided. The method begins withprovision of a semiconductor processing component having an outersurface portion formed by chemical vapor deposition of silicon carbide,the outer surface portion having a bulk impurity level and a surfaceimpurity level. Further, a target portion of the outer surface portionis removed, such that the surface impurity level is not greater thanabout ten times the bulk impurity level.

[0010] Still further, according to another embodiment, a method fortreating a semiconductor processing component is provided. The methodbegins with provision of a semiconductor processing component having anouter surface portion formed by chemical vapor deposition of siliconcarbide. The outer surface portion has a bulk impurity level and asurface impurity level. Further, the method continues with removal of atarget portion of the outer surface portion, such that the surfaceimpurity level is reduced by a factor of at least ten.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The present invention may be better understood, and its numerousfeatures and advantages made apparent to those skilled in the art byreferencing the accompanying drawings.

[0012]FIG. 1 illustrates an embodiment of the present invention, namelya wafer boat or carrier.

[0013]FIGS. 2 and 3 illustrate the impurity depth profile of CVD-SiCfilms formed in two different commercially available depositionapparatuses.

[0014]FIG. 4 illustrates the impurity depth profile of CVD-SiC, formedutilizing reactant gases at higher contaminant levels.

[0015]FIG. 5 illustrates the impurity depth profile of a CVD-SiC layerbefore and after an initial cleaning step.

[0016]FIG. 6 illustrates a depth profile resulting from two cleaningcycles of another sample, having a relatively low-purity CVD-SiC layer.

[0017] The use of the same reference symbols in different drawingsindicates similar or identical items.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

[0018] According to aspects of the present invention, a semiconductorprocessing component, and a method for treating a semiconductorprocessing component are provided. The semiconductor processingcomponent generally is formed at least partially of SiC, including anouter surface portion that has a controlled impurity content. The outersurface portion is typically formed by chemical vapor deposition (CVD),and has an outer purity that is not greater than ten times a bulkpurity. The outer surface portion may be defined as an identifiable SiClayer formed by CVD, or an outer thickness of a SiC component formedprincipally by CVD, as in the case of free-standing CVD-SiC components,described in more detail below.

[0019] According to one aspect, the present inventors have recognizedthat as-deposited CVD-SiC has a spike in impurity levels at the outersurface thereof, typically within the first 0.5 μm, such as within thefirst 0.25 μm, or the first 0.10 μm of the outer depth of the component.While, in contrast, the impurity level through the bulk of the outersurface portion stabilizes at a relatively low level, oftentimes one,two, or even three orders of magnitude lower than an impurity level atthe very outer surface of the component. The bulk impurity level isgenerally that impurity level which represents the constant or nominalimpurity level as a function of depth, and is further describedhereinbelow. The foregoing a phenomenon is generally not recognized inthe art, and rigorous analysis of as-deposited CVD-SiC layers hasrevealed a significant spread in impurity levels. Impurity levels aregenerally based on at least one of or a combination of Cr, Fe, Cu, NiAl, Ca, Na, Zn, and Ti concentrations, between the outer surface and thebulk portion of the outer surface portion. According to an embodiment,the impurity levels are based on one of or both Fe and Cr.

[0020] In this context, according to another embodiment of the presentinvention, a semiconductor processing component having an outer surfaceportion formed by chemical vapor deposition of SiC is provided, and atarget portion of the outer surface portion is removed, such that asurface impurity level of the outer surface portion is not greater thanabout ten times the bulk impurity level of the outer surface portion.While a maximum 10× difference in impurity levels between the bulk andthe surface is generally desired, further embodiments have a surfaceimpurity level that is not greater than about five times, such as notgreater than about two times the bulk impurity level. Indeed, certainembodiments have a surface impurity level that is not greater than thebulk impurity level.

[0021] The semiconductor processing component according to embodimentsherein may be chosen from one of various geometric configurations fordifferent processing operations, and may be configured for receivingvarious sized wafers, whether 150 mm, 200 mm, or newer generation 300 mmwafers, for example. Particular processing components includesemiconductor wafer paddles, process tubes, wafer boats, liners,pedestals, long boats, cantilever rods, wafer carriers, vertical processchambers, and even dummy wafers. Of the foregoing, several of thesemiconductor processing components may be those that are configured fordirect contact with and for receiving semiconductor wafers such ashorizontal or vertical wafer boats, long boats, and wafer susceptors. Inaddition, the processing component may be configured for single waferprocessing and may be used for chambers, focus rings, suspension rings,susceptors, pedestals, etc.

[0022] The semiconductor processing component may be fabricated byvarious techniques. For example, according to one embodiment, theprocessing component is formed by provision of a substrate that isgenerally coated with a SiC layer by CVD. The CVD-SiC layer mayadvantageously function to attenuate auto-doping of the underlyingsilicon, as well as prevent migration of impurities from the bulk of thesubstrate to an outer surface of the component, which may lead tocontamination during semiconductor wafer processing. The substratetypically functions to provide mechanical support and structuralintegrity, and may be formed of various materials, such asrecrystallized SiC, and by various processing pathways. In onetechnique, the substrate, primarily composed of SiC, is formed by slipcasting or by pressing. In the case of slip casting, the slip-cast bodyis dried and heat treated, followed optionally by impregnation to reduceporosity. Advantageously, impregnation may be carried out byinfiltration with molten silicon. Other specialized fabricationtechniques may also be used, such as by utilizing a conversion processin which a carbon preform is converted into a silicon carbide core, orby subtractive process in which the core is removed followinginfiltration, such as by chemical vapor infiltration.

[0023] Alternatively, the semiconductor processing component may beformed of stand-alone silicon carbide, formed of one of variousprocesses such as by CVD of silicon carbide. This particular processtechnique enables formation of a processing component that is ofrelatively high purity throughout substantially the entire bulk orinterior portion of the component.

[0024] An embodiment of a wafer processing component is shown in FIG. 1.Wafer boat 1 illustrated in FIG. 1 has a plurality of grooves 16, eachof which extends along the same radius of curvature. Each groove has anindividual groove segment 18, 20 and 22, which are desirably machinedfollowing fabrication of the wafer boat proper. For example, the waferboat may be fabricated according to one of the techniques describedabove, such as by impregnating a silicon carbide core with moltenelemental silicon, then executing CVD to form a deposited siliconcarbide layer. Following formation of the silicon carbide layer,machining may be carried out. In particular, the grooves may be formedand fine dimensional control may be executed by a machining operation,such as by utilizing a diamond-based machining tool. Noteworthy, whileFIG. 1 illustrates a horizontal wafer boat, it is to be understood thatvertical wafer boats or wafer carriers may be utilized as well, as wellas other semiconductor processing components as already mentioned.

[0025] Following formation of the processing component, the processingcomponent is subjected to a treatment process. Namely, the outer portionof the component formed of CVD-SiC is manipulated to improve purity, andparticularly, the impurity of the outer surface. In one embodiment, atarget portion of the outer surface portion is removed, leaving behindan outer surface that has an impurity content that is not greater thanten times that of a bulk impurity content of the outer surface portion.

[0026] Removal of the target portion may be carried out by any one ofseveral techniques. According to one technique, the outer surfaceportion is removed by an oxidation-stripping process. During oxidation,the component may be exposed to a reactant species, such as a halogengas, to further improve purity. The reactant species generally functionsto complex or react with existing impurities, and volatilize during hightemperature treatment. Oxidation-stripping may also reduce particlecount along the outer surface, particularly beneficial in the context ofsemiconductor processing operations.

[0027] In more detail, oxidation of the semiconductor processingcomponent is generally carried out to form an oxide layer by chemicalreaction to form a conversion layer, as opposed to a deposited oxidelayer. According to the oxidation treatment, an oxide layer consumes atarget portion of the component, namely a portion of the CVD-SiCmaterial. The oxide layer may be formed by oxidation of the component inan oxidizing environment, such as by oxidizing the component in anoxygen containing environment at an elevated temperature, such as withina range of 950 to about 1300 degrees C., and more specifically in arange of about 1000 to about 1250 degrees C. Oxidation may be carriedout in a dry or wet ambient, and is typically carried out at atmosphericpressure. A wet ambient can be generated by introducing steam, andfunctions to increase the rate of oxidation. The oxide layer isgenerally silicon oxide, typically SiO₂. The silicon oxide layer may bein direct contact with the silicon carbide of the component, as in thecase of free-standing SiC or substrates coated with silicon carbide,such as by CVD.

[0028] The oxide layer may cause residual silicon carbide particulatesto be converted to silicon oxide, in addition to formation of an oxidelayer along the body proper. In the case of particulate conversion,oxidation may enable later stage particulate removal. In addition,formation of an oxide coating by a conversion process, rather than adeposition process, helps trap residual impurities, such as metallicimpurities, within the oxide layer, for removal along with stripping ofthe oxide layer.

[0029] The oxide layer may be stripped by exposure of the processingcomponent to a solution that is capable of solubilizing (dissolving) theoxide layer. In one embodiment, the solution is an acid which containsfluorine. Typically, the pH of the solution is less than about 3.5, mosttypically less than about 3.0, with some embodiments being even moreacidic, having a pH less than about 2.5. Alternatively, the solution maybe basic, and exposed to the layer in conjunction with elevatedtemperatures (greater than room temp, but below H2O boiling point).Alternatively, high temperature and H2 gas, such as above 1000° C., mayalso be used.

[0030] During oxidation, the semiconductor processing component may beexposed to a reactive species, such as a halogen gas, that forms areaction product with contaminants present at the outer surface of theouter surface portion. Generally, both the exposure to a reactivespecies and oxidizing are carried out simultaneously, althoughalternatively the steps may be carried out separately. In this regard,use of the term simultaneously does not require that the exposure andoxidation steps to be carried out so as to be completely coextensive,but rather, the steps may overlap each other partially.

[0031] The term “halogen gas” denotes use of any halogen group elementsprovided in gaseous form, typically combined with a cation. An exampleof a common halogen gas which may be employed according to embodimentsof the present invention includes HCl. Other gasses include those thatcontain fluorine, for example. Typically, the elevated temperature atwhich the semiconductor processing component is exposed to the halogengas is sufficient to enable a reaction between the halogen gas andimpurities contained along an outer surface portion of the semiconductorprocessing component, including along the exposed outer surface of thesemiconductor processing component. For example, the elevatedtemperature may be within a range of about 950° C. to about 1300° C.Further, the concentration of the halogen gas may vary, and may bepresent in the heated environment (e.g., a furnace processing chamber)within a range of about 0.01 to about 10% of the total pressure.Typically, the lower limit of the partial pressure is somewhat higher,such as about 0.05, or about 0.10%. While the foregoing has focusedhalogen gases, other reactive anion-containing reactants may beutilized, provided that the reactant is chosen so as to form a reactionproduct with expected metallic impurities, and that the reaction producthas a higher volatility than that of the metallic impurity itself.

[0032] Typically, the impurity with which the halogen gas reacts alongan outer surface portion of the semiconductor processing component is ametal impurity. Metal impurities may take on the form of elementalmetal, or metal alloys, and may be aluminum-based, iron-based, orchromium-based, for example. The use of a halogen gas such as HCl causesthe formation of a reaction product with such metal impurities. Thereaction product typically has a higher volatilization than theimpurities, such that during the exposure of the processing component tothe elevated temperature, the reaction product volatilizes and is thusremoved from the processing component.

[0033] While the above disclosure has focused on removal of a portion ofthe component by reacting, notably by oxidation-stripping, othertechniques for removing the target portion may be utilized. For example,the target portion may be reacted by an etching operation, byintroducing an etchant species at an elevated temperature to form anetchant product that volatilizes to wholly or partly remove the targetportion. For example, the etchant species may be a chlorine-containinggas, forming SiCl_(x) etchant product that volatilizes. TheCl-containing gas may be HCl, Cl₂, and others. In some cases, carbon maybe left behind as a by-product of the etching operation. This carbon maybe removed by a high temperature bum-out treatment. It is noted thatsometimes etching is referred to as graphitization, describing thecarbon in the form of graphite left behind on the surface of thecomponent. It is also generally desirable that the etchant usedcomplexes with the impurities present along the outer surface portion,forming volatilized species such as FeCl, TiCl, etc. Further, asdescribed above, to the extent that oxidation and oxide stripping areutilized to remove the target portion, the contaminants may be reactedto form a reaction product, such as by introducing a halogen gas asalready described above in detail.

[0034] Prior to removal of the target portion by any of the techniquesdisclosed herein, the component may be subjected to a machiningoperation, to remove, for example 10 to 100 microns of outer material ofthe component. While the as-deposited impurity profile is generallyaltered by material removal from machining operations, machining tendsto nevertheless leave a spike in impurities at the outer surface of thecomponent (i.e., the as-machined surface), as similarly observed inas-deposited CVD SiC. It has been found that the surface impurity levelmay extend into the outer surface portion, such as on the order of 1-3microns, before reaching the bulk impurity level. Accordingly, inembodiments that have been subjected to machining, oftentimes the targetportion to be removed has a thickness at the higher end of the abovenoted range of up to about 20 microns, with actual thicknesses removedon the order of 3 to 5 microns. Accordingly, to the extent that theCVD-SiC surface of the component is subjected to a mechanical abrasionor machining process such as grinding, lapping or polishing, prior toremoval of the target portion, further removal would generally beeffected due to elevated contamination levels present in thepost-machined surface. Removal of the target portion may executed withoxidation-strip cycles or etching cycles, for example, carried outenough times to effect high purity.

[0035] According to another feature, removal of the target portion iscarried out prior to use of the processing component in a semiconductorfabrication environment. As such, the foregoing steps may be carried outoff-site, separate from the semiconductor fabrication environment, suchas by the manufacturer of the processing component rather than the enduser (e.g., the semiconductor component manufacturer/wafer processor).The processing component may be fully treated, then packaged in ahermetic shipping container for direct and immediate use in afabrication environment. While the foregoing has focused on one cycle,processing steps such as oxidation-steps (with optional halogen gastreatment) may be repeated, and is generally repeated, several times toachieve the desired level of purity through removal of the targetportion.

[0036] According to a variant, additional processing steps may beincorporated prior to target portion removal, with an aim to furtherreduce impurity levels. For example, the component may be rinsed, suchas with deionized (DI) water, prior to exposure to halogen gas andsubsequent processing. Agitation may be carried out during rinsing, suchas with an ultrasonic mixer/agitator, to further supplement contaminantremoval. Further, the rinsing solution may be acidic solution to aid instripping the contaminants.

[0037] Alternatively, or in addition to rinsing, the component may beimmersed in an acidic stripping solution prior to halogen speciesexposure, such as an acidic solution, to further aid in impurityremoval. The rinsing and/or immersion steps may be repeated any numberof times prior to further processing.

[0038] Due to the observed depth profiling as described in more detailbelow, typically the target portion has a thickness of at least about0.25 microns, such as 0.38 microns, 0.50 microns, and even higher.Indeed, the target portion most generally has a thickness of at least1.0 microns, and preferably at least about 2, such as about 2-10 micronsmicrons, but generally less than 20 microns. Typically the CVD-SiC layerhas a thickness with a range of about 10 to 1000 μm, and certainembodiments have a thickness up to about 800 μm, 600 μm, 400 μm, or upto about 200 μm. The thickness of the target portion corresponding tothe depth of removal of the outer surface portion of the component isgenerally chosen to ensure the desired surface impurity reduction, suchas driving the impurity content down from 1,000× of bulk to on the orderof 10× of bulk, or even lower. Indeed, the surface impurity level isgenerally reduced by at least one order of magnitude if not two ordersof magnitude as a result of the removal of the target portion.

[0039] With respect to the particular measurement techniques forcharacterizing pre- and post-treated CVD-SiC films, particular use ismade of Secondary Ion Mass Spectroscopy (SIMS). Other techniques includeGDMS, for example. As used herein, the bulk impurity level generallycorresponds to the impurity level at a depth within the outer surfaceportion at which the purity level is stabilized, that is, is generallyconstant further into the depth of the outer surface portion. It isnoted that impurity detection usually entails some degree of variance,represented by swings in measured impurity levels as a function ofdepth. Unless otherwise noted herein, while raw data is reported,specific impurity level data points, and particularly the bulk impuritylevel, are based upon a trend of the impurity contents according to thedata, that is, smoothed data. According to characterization studiesreported herein, it was found that typically the bulk impurity level istypically reached by a depth of 3 microns. Accordingly, the bulkimpurity level may be taken at a depth within a range of about 3 to 10μm, such as within a range of 3 to 5 μm, for example. The particulardepth value at which the bulk impurity level is reached, however, may bedependent on processing conditions of the particular CVD processutilized to form the outer surface portion, including particular toolused, gases used, temperature, pressure, and other processingparameters.

[0040] According to a particular embodiment, the bulk impurity level isnot greater than about 1e17 atoms/cc iron (Fe) and not greater than 1e15atoms/cc chromium (Cr). Of course, more demanding end use applicationsof processing components may call for even lower bulk impurity levelsthan the foregoing, such as 1e16 atoms/cc iron (Fe).

[0041] The data and following discussion focus on characterizationstudies done on several as-deposited CVD-SiC samples as well as onpost-treated CVD-SiC samples.

[0042] Si:SiC coupons of size 25 mm×75 mm×6 mm were prepared usingstandard processing. The coupons were ultrasonically cleaned in diluteacid, DI water rinsed, and dried. The cleaned coupons were loaded intothe CVD reactor and a CVD film between 12-18 microns in thickness wasdeposited on the surface of the Si:SiC coupons. Multiple coating runswere performed using two different coating systems (Apparatus A andApparatus B) to further understand equipment effects on coating purity.

[0043] The impurity level on the surface of the CVD coated Si:SiCcoupons was analyzed by Secondary Ion Mass Spectroscopy (SIMS). The SIMSanalysis was conducted with O₂ ⁺ plasma using a Cameca 3f instrument ina depth profile mode. The instrument was calibrated using ion implantedSiC standards for accurate impurity determination. The analysis wasfocused on Fe and Cr alone to enable a good detection limit, viz. 1e15atoms/cc for Fe and 1e14 atoms/cc for Cr. Unless otherwise noted, theresults described hereinafter represent as-deposited or as-removedCVD-SiC, with no intermediate machining operations.

[0044] The SIMS analysis of the CVD-SiC layer of a sample processed byApparatus A, indicates a high surface contamination of both Fe and Crthat is 500-1000 times higher than the bulk value as shown in FIG. 2.The Fe concentration in the bulk is <1e15 atoms/cc and the Crconcentration is <1e14 atoms/cc, which is typical for CVD-SiC coatings.

[0045] A similar high surface impurity concentration was also observedon the CVD-SiC layer deposited using Apparatus B, as shown in FIG. 3.

[0046] The surface Fe concentration is >1e18 atoms/cc and drops to thebulk value of <1e15 atoms/cc within 0.5 microns depth into the CVD-SiCcoating for the particular samples under characterization. To verify theuniversality of high impurity concentration on the surface ofas-deposited coatings, a third test was conducted on a CVD-SiC coatingwith higher impurities in the reactant gases used to form the CVD film.Impurity enrichment was also observed on coatings with higher impuritylevels as shown in FIG. 4. The Fe concentration at the surface is >1e19atoms/cc, and drops over 2-2.5 microns to the bulk Fe concentration of 5e16 atoms/cc. The Cr at the surface is 5e17 atoms/cc, which is a factorof 550 higher than the bulk Cr concentration of 7e14 atoms/cc. Therelatively gradual drop in impurity concentration from the surface tothe bulk may be related to differences in surface roughness between thecoatings under characterization.

[0047] Mechanisms for impurity enrichment at the surface are not wellunderstood at the present but may relate to impurity migration from thesurface of the Si:SiC substrate during the CVD-SiC deposition process orFe segregation from the interior of the film to the surface duringcooling.

[0048] Two different types of CVD-SiC coatings were produced withApparatus A, a standard coating and a lower-purity coating, wereselected for cleaning processing. The coupons were loaded onto a CVDcoated cantilever paddle and placed into a diffusion furnace equippedwith a SiC process tube.

[0049] The coupons were oxidized at 950-1350° C. for 6-14 hours inflowing O2 with up to 10% HCl gas. The thermal treatment conditions wereselected to enable the growth of a thick thermal oxide on the CVD-SiCsurface through consumption of a target portion of the CVD-SiCcorresponding to about 0.45-0.60, nominally 0.5 times the thickness ofthe oxide. The oxidation process helps to concentrate the transitionmetal impurities such as Fe into the oxide layer on the CVD-SiC. Whilethe HCl gas helps to volatilize the impurities on the surface of thegrowing oxide, HCl treatment is not believed to significantly removemetal trapped within the growing oxide layer. The overall processconsumes the contaminated target portion of the CVD-SiC layer throughthe reaction, SiC+{fraction (3/2)}O2 (g)=SiO2+CO(g) to form SiO2.

[0050] To remove the bulk impurities within the oxide layer, the oxidelayer was stripped in an acid bath using a HF-HCl mixture (1:1 acidmixture). The resulting impurity concentration at the surface is shownin FIG. 5.

[0051] SIMS analysis indicates that the surface Fe concentrationdecreases from >5e17 atoms/cc on the initial CVD-SiC coupon to <5e16atoms/cc on the cleaned coupon, a 10 fold improvement due to cleaning.The bulk impurity concentration remained constant at <1e15 atoms/cc.While the cleaning cycle decreased surface impurity concentration, thesurface impurity concentration was still a factor of 50 higher than thebulk. Thus, an additional cleaning cycle was conducted to furtherdecrease the Fe concentration at the surface. The effect of the 2^(nd)cleaning cycle could not be quantified using SIMS due to detection limitissues and noise in the analysis. Accordingly the cleaning cycles wererepeated using the CVD-SiC sample with higher impurities (shown in FIG.4) to help discern minor differences between the surface and bulkimpurity levels.

[0052] The lower purity CVD-SiC sample was cleaned similar to thestandard CVD-SiC sample. The coupons were first oxidized at 950-1350° C.for 6-14 hours in flowing O2 with up to 10% HCl gas to grow an oxidelayer that was subsequently stripped by the HF-HCl solution. Thecleaning cycle was repeated a second time to remove material deeper intothe CVD-SiC surface and thereby remove the Fe-enriched surface layer.

[0053] SIMS analysis of coupons after two cleaning cycles is shown inFIG. 6. The double cleaning cycle was effective to completely remove thecontaminated surface layer, and the surface impurity concentration issimilar to the bulk impurity concentration.

[0054] It is again noted that, while the foregoing characterizationstudies have taken advantage of repeated oxidation-strip cycles coupledwith halogen gas treatment, other removal techniques may be employed forremoval of the target portion. Further, it has been found that repeatedremoval steps may be carried out in order to drive the surface impuritylevels to a desirable range as described above, a single cycle resultedin a surface impurity level that was dramatically improved, but stillhaving an impurity level that was 50× that of the bulk. Accordingly,repeated cycles are generally carried out to ensure bulk-like purity atthe surface.

[0055] Still further, as demonstrated by FIG. 6, the techniquesdescribed herein may be carried out to reduce the impurity level of thesurface to be not greater than the bulk impurity level, that is, aboutequal to or less than the bulk impurity level. Note that the data shownin FIG. 6 were taken from two different samples, and are provided forcomparative purposes to show impurity trends before and after treatment.

[0056] The above-disclosed subject matter is to be construed asillustrative and not restrictive, and the appended claims are intendedto cover all such modifications, enhancements, and other embodimentsthat fall within the scope of the present invention. Thus, to themaximum extent allowed by law, the scope of the present invention is tobe determined by the broadest permissible interpretation of thefollowing claims and their equivalents and shall not be restricted orlimited by the foregoing detailed description.

What is claimed is:
 1. A semiconductor processing component comprisingSiC, wherein an outer surface portion of the component has a surfaceimpurity level that is not greater than 10 times a bulk impurity level.2. The component of claim 1, wherein the bulk impurity level is measuredat a depth of at least 3 μm from an outer surface of the outer surfaceportion.
 3. The component of claim 1, wherein the outer surface portionis comprised of CVD-SiC.
 4. The component of claim 3, wherein the outersurface portion is a CVD-SiC layer deposited over a substrate.
 5. Thecomponent of claim 4, wherein the substrate comprises SiC.
 6. Thecomponent of claim 5, wherein the substrate comprises SiC impregnatedwith elemental silicon.
 7. The component of claim 6, wherein thesubstrate comprises recrystallized SiC impregnated with elementalsilicon.
 8. The component of claim 4, wherein the CVD-SiC layer has athickness within a range of about 10 to about 1000 μm.
 9. The componentof claim 4, wherein the CVD-SiC layer has a thickness within a range ofabout 10 to about 800 μm.
 10. The component of claim 3, wherein thecomponent is a free-standing CVD-SiC component.
 11. The component ofclaim 10, wherein the component consists essentially of CVD-SiC.
 12. Thecomponent of claim 1, wherein the surface impurity level is not greaterthan 5 times the bulk impurity level.
 13. The component of claim 1,wherein the surface impurity level is not greater than 2 times the bulkimpurity level.
 14. The component of claim 1, wherein the surfaceimpurity level is not greater than the bulk impurity level.
 15. Thecomponent of claim 1, wherein the surface impurity and bulk impuritylevels are based on at least one of Cr, Fe, Cu, Ni Al, Ca, Na, Zn, andTi concentrations
 16. The component of claim 15, wherein the surfaceimpurity and bulk impurity levels are based on at least one of Cr and Feconcentrations.
 17. The component of claim 16, wherein the surfaceimpurity and bulk impurity levels are based on Fe concentration.
 18. Thecomponent of claim 16, wherein the bulk impurity level is not greaterthan 1E17 atoms/cc Fe and not greater than 1E15 atoms/cc Cr.
 19. Thecomponent of claim 1, wherein the semiconductor processing componentcomprises a component from the group consisting of semiconductor waferpaddles, process tubes, wafer boats, liners, pedestals, long boats,cantilever rods, wafer carriers, process chambers, dummy wafers, wafersusceptors, focus rings, suspension rings.
 20. The component of claim19, wherein the component is a wafer boat.
 21. The component of claim 1,wherein the component is machined prior to treatment to provide saidsurface impurity level.
 22. A method for treating a semiconductorprocessing component, comprising: providing a semiconductor processingcomponent having an outer surface portion formed by chemical vapordeposition of SiC, the outer surface portion having a bulk impuritylevel and a surface impurity level; and removing a target portion of theouter surface portion, such that the surface impurity level is notgreater than 10 times the bulk impurity level.
 23. The method of claim22, wherein the surface impurity level is not greater than 5 times thebulk impurity level.
 24. The method of claim 22, wherein the surfaceimpurity level is not greater than 2 times the bulk impurity level. 25.The method of claim 22, wherein the surface impurity level is notgreater than the bulk impurity level.
 26. The method of claim 22,wherein the target portion is removed by reacting the target portion.27. The method of claim 26, wherein reacting is oxidizing such that theouter surface portion forms an oxide, and the step of removing thetarget portion further includes removal of the oxide.
 28. The method ofclaim 27, wherein oxidizing and removal of the oxide are repeated toremove said target portion.
 29. The method of claim 27, wherein the stepof oxidizing is carried out at a temperature within a range of about 950to about 1300 degrees C.
 30. The method of claim 27, wherein the step ofoxidizing is carried out in a wet ambient atmosphere.
 31. The method ofclaim 26, wherein the target portion is removed by etching.
 32. Themethod of claim 31, wherein etching includes reacting the target portionwith an etchant species to form an etchant product, the etchant productvolatilizing to remove the target portion.
 33. The method of claim 32,wherein the etchant species is a Cl-containing gas, forming a SiCl_(x)etchant product.
 34. The method of claim 22, further comprising reactingcontaminants present at an outer surface of the outer surface portion toform a reaction product.
 35. The method of claim 34, wherein the targetportion is removed by oxidizing the outer surface portion to form anoxide followed by removal of the oxide, and the steps of reacting andoxidizing are carried out simultaneously.
 36. The method of claim 34,wherein the reaction product volatilizes after formation, improvingpurity of the component.
 37. The method of claim 34, wherein thereaction product has a higher volatility than the contaminant.
 38. Themethod of claim 34, wherein the contaminants are reacted with a halogengas.
 39. The method of claim 34, wherein the halogen gas comprises ahalogen from the group consisting of chlorine and fluorine.
 40. Themethod of claim 39, wherein the halogen gas comprises HCl.
 41. Themethod of claim 38, wherein the halogen gas is present at a partialpressure within a range of about 0.01 to about 10%.
 42. The method ofclaim 22, wherein the semiconductor processing component comprises acomponent from the group consisting of semiconductor wafer paddles,process tubes, wafer boats, liners, pedestals, long boats, cantileverrods, wafer carriers, process chambers, dummy wafers, wafer susceptors,focus rings, suspension rings.
 43. The method of claim 22, wherein thesemiconductor processing component comprises a substrate, the outersurface portion being a coating overlying the substrate.
 44. The methodof claim 43, wherein the substrate comprises elemental silicon.
 45. Themethod of claim 44, wherein the substrate comprises silicon carbide withsaid elemental silicon impregnated thereon.
 46. The method of claim 22,wherein the target portion is removed prior to use in a semiconductorprocessing operation.
 47. The method of claim 22, wherein target portionis removed by repeating removal steps.
 48. The method of claim 22,wherein the target portion has a thickness of at least 0.25 μm.
 49. Themethod of claim 22, wherein the target portion has a thickness of atleast 0.38 μm.
 50. The method of claim 22, wherein the target portionhas a thickness of at least 0.50 μm.
 51. The method of claim 22, furthercomprising machining the component prior to removing of the targetportion.
 52. A method for treating a semiconductor processing component,comprising: providing a semiconductor processing component having anouter surface portion formed by chemical vapor deposition of SiC, theouter surface portion having a bulk impurity level and a surfaceimpurity level; and removing a target portion of the outer surfaceportion, such that the surface impurity level is reduced at least 10×.53. The method of claim 52, wherein the surface impurity level isreduced at least 100×.